Computer Logic Design Lab

VHDL Lectures Fall 2007

(click here)

 

 

The following are the solution of the tests for Fall 2007:

Exam 1

 

 

The following are the solution of the tests for Spring 2006:

Exam 1

Exam 2

 

 

The following are the solution of the tests for fall 2005:

Exam 1

Exam 2

The following are lecture notes prepared by Prof. Marios Pattichis.

VHDL Lecture notes

The following are lecture notes based on the text book (Logic and Computer Design Fundamentals by Mano and Kime). These are scaned notes that can be used as an additional reference. You will also find tipical tests.

 

Test Examples

 

" Older Exams"

 

1. Exam One Practice (8 different exams!!)
2. Exam Two Practice (8 different exams!!)
3. Final Practice The pictures referenced have change between book editions. In the Third Edition, Figure 7.7 is now 7.20; figure 7.9 is now 10.1; figure 7.17 is now 10.9; figure 8.2 is now 8.19; for figure 7.9 click here (pdf) or here (jpg); figure 8.6 and 8.7 are the same.
4. More problems
5. Some lectures notes
6. More questions
7. Another exam2 solutions

 

Module 1 : Chapters 1 and 2

1. Lecture one:
   • Chapter 1:Sections 1-3, Digital Computers and number systems
2. Lecture two:
   • Chapter 1: Section 3, Number Base Conversion
3. Lecture three:
   • Chapter 1: Sections 3&4, Decimal Conversion and BCD addition
4. Lecture four:
   • Chapter 2: Sections 1-2, Boolean Algebra
5. Lecture five:
   • Chapter 2 Section 6, Gates
6. Lecture six:
   • Chapter 2, Section 3, Canonical Expressions
7. Lecture seven:
   • Chapter 2, Section 5, K-Maps
8. Lecture eight:
   • Chapter 2, Section 7, Exclusive OR (XOR)
9. Lecture nine:
   • Chapter 2, Section 8, Integrated Circuits

Module 2: Chapters 3 and 4

1. Lecture ten:
   • Chapter 3, Sections 1-4, Design Heiarchy and Analysis
2. Lecture eleven:
   • Chapter 3, Sections 5-6, Decoders and Encoders
3. Lecture twelve:
   • Chapter 3, Sections 7-8, Multiplexers and Adders
4. Lecture thirteen:
   • Chapter 3, Sections 9-10, Binary Subtraction and 2's Compliment
5. Lecture fourteen:
   • Chapter 3, Section 8, Carry and Look Ahead Adder
6. Lecture sixteen:
   • Chapter 4, Sections 1-3, Latches and Flip Flops
7. Lecture seventeen:
   • Chapter 4, Section 4, Sequential Circuit Analysis, Mealy/Moore Models
8. Lecture eighteen:
   • Chapter 4, Section 5, Sequential Circuit Design
9. Lecture ninteen:
   • Mealy/Moore Design Circuits
10. Lecture twenty:
    • Mealy vs. Moore Design

Module 3: Chapters 5 and 6

1. Lecture twenty one :
   • Chapter 5, Sections 1-5, Registers and Counters
2. Lecture twenty two :
   • Chapter 5, Sections 6, BCD Counters
3. Lecture twenty three :
   • Chapter 6, Sections 1-2, Memory and Programmable Logic Devices
4. Lecture twenty four :
   • Chapter 6, Sections 3-8, RAM and Programmable Logic Arrays

Module 4: Chapters 7 and 8

1. Lecture twenty five :
   • Chapter 7, Sections 1-7, Register Transfers
2. Lecture twenty six :
   • Chapter 7, Sections 8-11, Data Path
3. Lecture twenty seven :
   • Chapter 8, Sections 1-4, Machine Sequencing and Contro