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Full Adder Objectives: 1. Develop a better understanding of a full adder. 2. To be able to recreate a circuit while being restricted to certain chips. 3. To design a circuit using Xilinx's CORE Generator and intregrating them into the creation of a project. This lab has two parts. The first is your traditional type of implementation through the use of silicon chips. The second part uses a new technology that Xilinx has created called a CORE Generator System. PART 1: Use NAND Gates to Implement Addition Although the lecture notes for Lab 4 talk about using a MUX, you are being asked to use NAND gates instead. a) Design a full adder, i.e., sum and carry, using only NAND gates and exclusive OR gates. b) There should be 3 inputs: A, B, and K (carry-in). c) There should be 2 outputs: C (carry-out) and S. d) Draw a layout diagram giving the relative position of the chips on the breadboard. e) Draw a logic diagram. f) Implement the circuits and verify the operation. PART 2: Use Xilinx's CORE Generator System to Implement Addition After implementing Lab 4's tutorial, create a fuller adder through the use of the CORE Generator in the Foundation 3.1i software. Use the "Registered Adder" that is listed on the Core Browser. Some helpful hints when designing this adder are: 1) carefully read the Data Sheet, 2) connect CLR to either zero or ground (GND) and, during testing, do not flatten the buses (this makes it easier to examine your results). The following deliverables are expected for PART 2 (the Xilinx portion): 1) A circuit schematic 2) A screen picture of it's simulation. 3) Define CE and explain what kind of signal does this input need. Why does CE need this kind of signal? 4) What is the range of the two data bus inputs? What about the output range? |
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