Site last updated
9/12/03

INTRODUCTION TO DIGITAL LOGIC

Objectives:
1.To design a simple circuit through the use of truth tables.
2.Familiarization with designing and testing (through the use of truth tables) circuits using silicon chips.
3.Familiarization with some of the Boolean Algebra theorems by implementing a few of them. 
4.Te get familiar with the Xilinx ISE tools for simulating, implementing, and testing a logic circuit.

For completion of this lab you will need to read and understand the Lab assignment.  The overall plan is to develop a knowledge for determining what the assignment calls for.  All logic will then be developed on paper.  For most of the first labs, there are two parts:  the physical part with 7400 chips and the Xilinx part.  A Lab Report will then be required from all students.  Go to Lab Report Layout for more information on lab report formats. 

The creation of the Xilinx portions of the lab will take time in the beginning.  As with any new software package, learning the ins and outs takes time and practice.  The ISE Sample Project from ISE Lab Introduction should help explain the necessary steps to get through the three small parts of Lab #1.

For Part 1, the code and testbench code are given.  Consequently, it is just a matter of following the procedures outlined in ISE Sample Project including the simulation.  Part 2 and Part 3 are a little bit more challenging because the code is not included, but with the example codes given so far, it should be easy enough to figure out.

Part 1:  Create a 2-Input NAND from a 3-Input NAND
The worksheet contains a truth table for the NAND functions (A * B)', (A * B * 0)', and (A * B * 1)'.  Fill out the entire truth table.  Based on what the results are, implement a 2-input NAND gate using a 3-input NAND gate.
(A)Design the circuit on paper using a 3-input NAND gate.  The inputs are A and B.  The output is F = (A * B)'.
(B)Draw a layout diagram giving the relative position of the chips on the breadboard.
(C)Draw a logic diagram.
(D)Develop the F = (A * B) circuit in Xilinx.  Using ISE Sample Project as your guide, paste the VHDL Code and the testbench code (found below) into a newly created project.
(E)Compare your simulation to your truth table.

NAND CODE                                       --*********************************************
-- File: Lab1_1.vhd
--
-- Purpose: This file is used to introduce students to the
-- functions of the NAND gate.  It uses two inputs and
-- one output.
--
-- Created:  8/1/02 TB
-- Modified:  8/1/02 TB
--Fixed comments
--
--*********************************************
--Defining the library packages to be used
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--Declaration of the module's inputs and outputs
--The modules name is "nand"
entity Lab1_1 is port (
A: in std_logic;
B: in std_logic;
Y: out std_logic
);
end Lab1_1;

--Defining, descriptively, the modules internal structure or behavior
architecture behavioral of Lab1_1 is
begin
fcn: process (A, B) begin
Y <= A NAND B;
end process;
end behavioral;

NAND TEST BENCH CODE
--*********************************************
-- File: Lab1_1_tb.vhd
--
-- Purpose: This file is used to test the Lab1_1 VHDL code.
-- It uses three inputs and one output.
--
-- Created:  8/1/02 CK JH TB
-- Modified:  8/15/02 TB
-- Fixed comments
--
--*********************************************
--Defining the library packages to be used
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_unsigned.all;
USE IEEE.STD_LOGIC_TEXTIO.ALL;
USE STD.TEXTIO.ALL;

--Declaration of ModelSim libraries use
--INTERNET STUDENTS ***using Modelsim XE comment out the next two lines.
--Regular lab students leave them as is.
LIBRARY UNISIM;
LIBRARY XILINXCORELIB;


ENTITY testbench IS
END testbench;

ARCHITECTURE testbench_arch OF testbench IS

COMPONENT Lab1_1
PORT (
a : in std_logic;
b : in std_logic;
y : out std_logic
);
END COMPONENT;

SIGNAL a : std_logic;
SIGNAL b : std_logic;
SIGNAL y : std_logic;

--Defining the variable "CLK_PERIOD" to be equal to 20 nano seconds
constant CLK_PERIOD : time:= 20 ns;

BEGIN
--Unit under test is the module nand. Notice that it is not case sensitive
UUT : Lab1_1
--Defining external interface signals. This associates ports of the named entity with
--signals in the current architecture.
PORT MAP (
a => a,
b => b,
y => y
);

--Three separate processes that provide for the three separate and distinct inputs.
--All three processes will run at the same time. A process is a collection
--of "sequential" statements executing in parallel with
--other concurrent statements or processes
--Clock for A
CLOCK: process
begin
a <= '0';
wait for CLK_PERIOD/2;
a <= '1';
wait for CLK_PERIOD/2;
end process;

--Clock for B
CLOCK2: process
begin
b <= '0';
wait for CLK_PERIOD;
b <= '1';
wait for CLK_PERIOD;
end process;

END testbench_arch;

Internet students use Winbreadboard to construct and simulate the circuit.  Regular students build the circuit on the logic trainer in the lab and demonstrate the circuit to the lab teaching assistant (TA) verifying that the circuit operation agrees with the truth table.

Part 2:  The Extention Theorem
This portion of the lab will verify Boolean algebra's extension theorem.  The equation is:
X + (X' Y) = (X + Y)
(A)Verify the above statement with the truth table found on the worksheet.
(B)Implement the circuit on paper using 2-input AND gates and 2-input OR gates.  The inputs are X and Y.  The two outputs are:  F1 = X + (X' Y)    and     F2 = (X + Y).  Use the same inputs for both circuits.
(C)Draw a layout diagram giving the relative position of the chips on the breadboard.
(D)Draw a logic diagram.
(E)Develop the circuit in Xilinx.  Create a new project and develop the VHDL Code and the testbench code using ISE Sample Project as your guide.
(F)Compare your simulation to your truth table.

Internet students use Winbreadboard to construct and simulate the circuit.  Regular students build the circuit on the logic trainer in the lab and demonstrate the circuit to the lab teaching assistant (TA) verifying that the circuit operation agrees with the truth table.

                                                                                                                             Part 3:  Self-Dual Theorem
(X + Y) (X' + Z) = X' Y + X Z
(A)Verify the above statement with the truth table found on the worksheet.
(B)Implement the circuit on paper using 2-input AND gates, 2-input OR gates, and NOT (inverter) gates.  The inputs are X, Y, and Z.  The two outputs are:  F1 = (X + Y) (X' + Z)    and    F2 = X' Y + X Z.  Use the same inputs for both circuits. 
(C)Draw a layout diagram giving the relative position of the chips on the breadboard.
(D)Develop the circuit in Xilinx.  As before, create a new project and develop the VHDL Code and the testbench code using ISE Sample Project as your guide.
(E)Compare your simulation to your truth table.

Internet students use Winbreadboard to construct and simulate the circuit.  Regular students build the circuit on the logic trainer in the lab and demonstrate the circuit to the lab teaching assistant (TA) verifying that the circuit operation agrees with the truth table.

                                                                                                                           Deliverables for LAB 1
Deliverables are the additional documentation that needs to be handed in along with the Lab Report.  For this and all following labs use Lab Report Layout as your guide.  In this lab include the following deliverables in your report to the TA:
1.A printed copy of the VHDL Code and the testbench code from Part 2 and Part 3.
2.A printed simulation waveform datasheet for Part 3 showing that the simulation coincides with the expected truth table of your function.  On the simulation, circle the point where all three inputs go "high" (5V).  To do a this use the "Print Screen" key on your keyboard and paste it into a word document.  
 

Click here to go to Lab 1 Worksheet.