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-- Company: 
-- Engineer: 
-- 
-- Create Date:    14:55:46 06/27/2011 
-- Design Name: 
-- Module Name:    selected_signal_assignment - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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-- ================================================================================
-- This code also demonstrates basic principles in VHDL, in particular, selected
-- signal assignment. Selected signal assignment (and conditional signal assignment)
-- statements also produce straight combinational code (like simple signal assignment)
-- Selected signal assignment is more powerful than simple signal assignment because
-- it adds 'choices' to the combinational circuit generated. 'Choices' are typically
-- represented in hardware as some sort of MUX or decoder. So in addition to 
-- combinational gates and functional units such as adders, multipliers, etc, which 
-- can be created by simple signal assignment stmts, selected signal assignment add
-- MUXs and decoders to the inputs and outputs to allow implementations that capture
-- the semantics of high level program constructs such as the 'if stmt' and 'case 
-- stmt'. Very useful constructs in an HDL (as they are in programming languages).
-- ================================================================================

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.all;

-- ================================================================================
-- The 'select_op' input signal is a single bit that is assigned the following 
-- meaning. When 'select_op' is '0', we will carry out addition on the two
-- operands 'combo_in1' and 'combo_in2'. When '1', we will multiply the low
-- order two bits of each operand to generate a 4 bit result. We will convert the
-- 'combo_xxx' bit vectors to signed value in 2's complement form before and
-- after carrying out the arithmetic operations.
entity selected_assignment is
   Port ( 
      select_op : in STD_LOGIC;
      combo_in1 : in STD_LOGIC_VECTOR(3 downto 0);
      combo_in2 : in STD_LOGIC_VECTOR(3 downto 0);
      combo_out : out  STD_LOGIC_VECTOR(3 downto 0));
end selected_assignment;

-- ================================================================================
-- Behavioral description follows.
architecture Behavioral of selected_assignment is
   signal op1, op2, op_out: signed(3 downto 0);
--   signal add_result, mult_result : std_logic_vector(3 downto 0);

   begin

-- The same disclosure is made here as was done for simple signal assignment, i.e.,
-- selected signal assignment is VERY useful for defining combinational 
-- circuits. Unfortunately, many students use 'process' blocks instead of simple 
-- assignment as shown below, and get into trouble when they don't follow the more 
-- complex rules associated with process blocks. In such cases, instead of 
-- generating combinational logic, the synthesis tool inserts 'hidden' latches, 
-- thereby adding unexpected sequential components and behavior. This NEVER occurs 
-- when using assignment -- you ALWAYS get combinational logic.

-- Create signed versions of the operands. Type conversion in VHDL is strict and
-- explicit. This is definitely a source of confusion and frustration for students,
-- even though the conversion routines are well documented. The best way to learn 
-- how to do this is to practice. It is not uncommon to use multiple conversion 
-- functions to get where you want to be. You should find a good reference for
-- these and bookmark it -- I still look them up and I've been coding VHDL for
-- over three years! NOTE: THESE CONVERSION functions REQUIRE the IEEE.NUMERIC_STD.all
-- package to be included above.

   op1 <= signed(combo_in1);
   op2 <= signed(combo_in2);

   with select_op select
      op_out <= op1 + op2 when '0',
                op1(1 downto 0) * op2(1 downto 0) when others;

   combo_out <= std_logic_vector(op_out);

end Behavioral;