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-- Company: 
-- Engineer: 
-- 
-- Create Date:    14:55:46 06/27/2011 
-- Design Name: 
-- Module Name:    simple_assignment - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
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-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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-- ================================================================================
-- The following is perhaps the most basic VHDL program one can devise. The VHDL
-- construct used is simple assignment, and the code is basically a textual
-- description of a graphical schematic you might create using AND, OR and
-- NOT gates.
-- ================================================================================

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.all;

-- ================================================================================
-- The four input port signals, 'combo_in', and two output port signals, 
-- 'combo_out', might connect to pushbuttons and LEDs, respectively, on an FPGA.
entity simple_assignment is
   Port ( 
      combo_in : in  STD_LOGIC_VECTOR(3 downto 0);
      combo_out : out  STD_LOGIC_VECTOR(1 downto 0));
end simple_assignment;

-- ================================================================================
-- Four 'local wires' are declared using the suffix 'lw' for internal wiring 
-- connections of the components.
architecture Behavioral of simple_assignment is
   signal lw1, lw2, lw3, lw4: std_logic;

   begin

-- Simple assignment, (as well as conditional and selected signal assignment to be 
-- demonstrated in other lab modules) is VERY useful for defining combinational 
-- circuits. Unfortunately, many students use 'process' blocks instead of simple 
-- assignment as shown below, and get into trouble when they don't follow the more 
-- complex rules associated with process blocks. In such cases, instead of 
-- generating combinational logic, the synthesis tool inserts 'hidden' latches, 
-- thereby adding unexpected sequential components and behavior. This NEVER occurs 
-- when using assignment -- you ALWAYS get combinational logic.

   lw1 <= combo_in(0) and not combo_in(1) and not combo_in(2) and not combo_in(3);
   lw2 <= not combo_in(0) and combo_in(1) and not combo_in(2) and not combo_in(3);
   lw3 <= not combo_in(0) and not combo_in(1) and combo_in(2) and not combo_in(3);
   lw4 <= not combo_in(0) and not combo_in(1) and not combo_in(2) and combo_in(3);

   combo_out(0) <= lw1 or lw2; 
   combo_out(1) <= lw3 or lw4; 

end Behavioral;