ECE 522: Hardware/Sofware Codesign with FPGAs
Instructor: Jim Plusquellic
DataFlow Software Implementation
DataFlow Hardware Implementation
Analysis of Control Flow and Data Flow I
Analysis of Control Flow and Data Flow II
Embedded Cores I
Embedded Cores II
Machine Learning Benchmarks
Learning and Classification Papers
!!!!!!!!!!!!!!!!!!!!!!! CLASS IS CANCELLED, WED. Nov 23rd !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
!!!!!!!!!!!!!!!!!!!!!!! CLASS IS CANCELLED, Mon. Nov 7th !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
9/27/2011: Please bring your laptops and boards to class tomorrow, Sept. 28th
9/14/2011: National Instruments holds a free instruction seminar every 3rd Thurs of the month (except Nov and Aug) at 11:30am at Ropers (Wyoming and Central). This includes a free lunch too! This Thur's topic is "What's new in Labview 2011". Also a good opportunity to network.
9/13/2011: Nexsy2 boards are due to arrive before class on Wed. Sept. 14. and will be handed out to you. I have about 6 Trendnet TU-s9 USB-Serial adapters that I can hand out. You may need to share these with your classmates until we get more. Hopefully, we'll have labview disks for you as well (see note below if you want to buy a copy).
9/9/2011: Brian to do HelloWorld demo on Sept. 12. Please bring you computers with EDK installed so you can follow along. You will be required to demo HelloWorld to me on Sept 19th (see lab0 below).
9/7/2011: PLEASE USE email@example.com for a license (not 1717@ as I indicated in class).
9/7/2011: Please install EDK by Friday morning (Sept. 9th). Please email me if you have any problems by noon, in case we need to visit Craig and Brian at COSMIAC.
"Below are the instructions to force XPS to realize of changes in the pcore hdl.
Link with solution:
- Right click on the Local Pcore that was imported (IP Catalog tab in XPS).
- Click on ''View MPD"
- Add to mpd file: OPTION ARCH_SUPPORT_MAP = (OTHERS=DEVELOPMENT) and save changes.
The status of your pcore should change from PRODUCTION to DEVELOPMENT.
- Every time you change your pcore be sure to "Rescan user repository" (Project option of the Menu).
Several of you have noted that you need to "clean hardware" in order for XPS to recognize changes that you have made to your VHDL code.
"I've been looking into why the Master self-test fails under the default settings. It turns out that Master Peripherals can only
access devices that are located on the PLB Bus. When the Data Memory (DLMB) is placed in Block RAM, it exists on a private bus (LMB
Bus) that is only accessible by the Microblaze. When we declare the Source and Destination Buffer in our C code they are
automatically placed in the data memory, which cannot be accessed by our peripheral. Mike's solution of placing everything in the
Micron memory works because it forces the data memory to exist in the Micron instead of Block RAM - and the Micron exists on the PLB
An alternative solution, if you still want to use Block RAM for the instruction and data memories (and therefore avoid using the XMD
console), is to comment out the existing declarations for the Source and Destination Buffers and instead declare two Xuint8 pointers
in "main" that you initialize to two addresses in the Micron memory. These pointers are then used to create the Source and
Destination Buffers. The C code looks like the below:
srcBufAddr = XPAR_MICRON_RAM_MEM0_BASEADDR;
dstBufAddr = (XPAR_MICRON_RAM_MEM0_BASEADDR + 1024);
"Self-test seems to be working fine for me. The self test fails when you use the default linker script settings. As long as you place
everything in Micron and increase the stack/heap to 0x800, then it should be fine."
Although this problem have been discussed in the class, I'm sending this email to you to help those students that have not been able
to compile the project yet.
It is needed to do these replacement in the "bus_master.c" and "bus_master.h" files to be able to compile the EDK project.
xil_io_in8 => Xil_In8
xil_io_in16 => Xil_In16
xil_io_out8 => Xil_Out8
xil_io_out16 => Xil_Out16
after these replacement I compiled the project several times but it seems that the EDK do not use the files that are in
"drivers\bus_master_v1_00_a\src" and also those that are in "microblaze_0\libsrc\bus_master_v1_00_a\src" folder so I copied these
files to the root folder of my project and I add them to my project, and after that I was able to compile the project.
But even after these modification the self test doesn't work properly. Now I'm trying to figure out what is wrong with the code."
"I checked the xil_io.h file and found that the function calls are actually
'Xil_Out8' instead of `xil_io_out8' and so on for the others. To fix this, I
modified the busmaster.c file located in the drivers folder, then in XPS ran the
Software->Clean Libraries selection, then Software->Generate Libraries and BSPs.
After this I was able to successfully build the project. I don't know if any
other students have run into this, but this is the reason why and a fix for it."
SDK Java engine crashes on startup. Fix by
1. Copy the libPortabilityNOSH.dll from the ISE/lib/nt64 directory to the EDK/lin/nt64 directory.
2. Rename the libPortabilityNOSH.dll file to libPortability.dll in the EDK/lin/nt64 directory.
PLEASE SEE INSTRUCTIONAL VIDEOS below for lab1. NOTE: THESE videos ASSUME YOU HAVE copied the digilent plugins into Xilinx/ISE_DS/ISE/lib/nt64/plugins/Digilent directory as per the instructions given below in Veronic's solution.
Veronica discovered on 9/25 how to deal with the external memory issue, where the C program is loaded in the external memory.
1. How to use XMD to download the executable.elf file
2. Download and Install Plugin:
3. From EDK Launch XMD (Debug option in Menu)
In terminal, copy and paste:
connect mb mdm -cable type xilinx_plugin modulename digilent_plugin
dow scan_and_print/executable.elf (dow name of the project/executable.elf)
When the last command "con" is entered, the executable.elf file gets executed on Microblaze.
Before running XMD, I test the plugins by downloading the download.bit file using Impact (instead of Adept, the instructions are in the first file).
Chip specs for ISE
9/26/2011: Kanamu points to a link that has a Quick Reference Card that NI for labview.
Kanamu pointed to a good tutorial on Labview at http://www.ni.com/academic/students/learnlabview/
LABVIEW VISA drivers (MUST INSTALL to get SERIAL port to work)
Please note that you will NOT be able to use the Xilinx program item 'Download Bitstream' with the USB cable and driver you are
using, namely the Digitent Adept driver. You must use the Adept software instead. Run it and select the download.bit file in the implementation directory.
Note that the download.bit file will only be present after you have completed the synthesis step cleanly (no errors). To generate a download.bit file,
as you probably know, is done by selecting 'Update Bitstream' in the same menu as the 'forbidden' Download Bitstream mentioned above.
We are working on getting a academic discount on the student version of Labview. Fareena checked yesterday and discovered that the bare bones version is only $20 if you decide to buy it. You won't need any of the bells and wistles of the more expensive $60 version.
You will also need to fetch the board file from http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,400,789&Prod=NEXYS2 in a separate download after you install Xilinx. You need to put the Digilent board files in the following directory on a windows machine:
Please be sure to RESTART EDK after you have done this.
Please install everything from the DVD handed out, including the Digitent Adept driver. Brian informs us that the Adept driver provides power to the Nexys2 board (so you don't need a power adapter), but in doing so, it disables the Xilinx tools, e.g., those used for debugging, etc. So if you want to use the Xilinx impact driver to retain this functionality, then you'll need to buy a power adapter.
John Vraines writes: "To get XPS to run, I also had to create a XILINX environment variable to the path of the ISE installation (...Xilinx\12.4\ISE_DS\ISE). Then it worked. Maybe it was just a bug with how the installer interacted with my machine by not creating that variable, but I figured I'd pass this along in case it was helpful."
Digilent Spartan 3E Board Documentation
Master UCF file for the Nexys2-1200
UNM EDK Tutorial (courtesy of Srikanth/Craig)
Trendnet TU-s9 USB-Serial adapter
Six hour LABVIEW tutorial (PDF)
Six hour LABVIEW tutorial (PPT)
Six hour LABVIEW exercises (DOC)
Six hour LABVIEW VIs (VIs)
Lession 1-4 LABVIEW course tutorial (PPT)
Lession 5-8 LABVIEW course tutorial (PPT)
Lession 9-11 LABVIEW course tutorial (PPT)
Test Switch Debouncer C code
EDK: Compile a new program (courtesy of Ryan)
EDK DOCUMENTATION LINK
Xilinx SUPPORT LINK
Ryan's UART polling example showing use of Uartlite I/O functions
Chip Scope Tutorial
Mitchell's web site that explains the installation of an embedded linux kernel
Xilinx EDK documentation:
XPS GPIO Data Sheet
XPS Interrupt Controller Data Sheet
C library functions for EDK (PDF)
My EDK doc
Demo 1: Base System Builder for EDK (AVI movie)
Demo 1: XPS Hardware Synthesis (AVI movie)
Demo 1: SDK Create Application (AVI movie)
Demo 1: Program FPGA from SDK (AVI movie)
Demo 2: Interrupt Demo Part I (AVI movie)
Demo 2: Interrupt Demo Part II (AVI movie)
Demo 3: EDK Tutorial 2: Create Peripherial (AVI movie)
Demo 3: EDK Tutorial 2: Import Peripherial (AVI movie)
Demo 3: EDK Tutorial 2: Make Connections (AVI movie)
Demo 3: EDK Tutorial 2: Add Software and Demo (AVI movie)
Lab 0 (Due: 9/19/2011)
Lab 1 (Due: 10/3/2011)
Lab 2 (Due: 10/12/2011)
John Vranes C code and UCF file for lab 2
My Interrupt C code for Pushbutton Interrupts, LED and UART LITE project for lab 2
My analysis of the TestApp Peripherial with Pushbutton Interrupts, LED and UART LITE for lab 2
Lab 3 (Due: 10/24/2011)
My analysis of the default user logic in a slave peripherial
Lab 4 (Due: 11/2/2011)
Lab 4 files
LAB 5: Read "Implementing Decision Trees in Hardware" (See Supplimentary Papers above, in particular StruharikDecisionTrees2011.pdf: Due 11/9/2011).
Jim Plusquellic /
Javad's pipelined 8051 as an example of a pipeline in VHDL (rar file)
Different C implements are in the net. Here are some of them.
The point that is common in these implementations is using dynamic memory allocation. So the problem of
implementing DT could be reduced to implementing a linked list in VHDL. There are some documents that
show how to do this.
http://www.eda.org/VIUF_proc/Fall96/BILIK96A.PDF (a paper)
http://enpub.fulton.asu.edu/cse517/advvhdl_subu.pdf (another paper)
http://www.fastertechnology.com/training-courses/xilinx-fpga-training-advanced-vhdl.html ( a course, Lab 2)
The designer's guide to VHDL, By Peter J. Ashenden ( a book, chapter 15)
Frank's data set in xls or cvs (text comma separated values) formats
My labview code for transferring a file to the FPGA. THIS NEEDS TO BE MODIFIED for your application. Right now, it reads an (x,y) floating point file, converts to integers, transfers, and then does the opposite on the data sent back. You should organize your text file as an (x,y,z) integer file and eliminate everything that deals with conversion between integer and floating point.
My C code for transferring a file to the host computer. THIS ALSO NEEDS TO BE MODIFIED for your application and the Spartan 3E boards.
"I found 3 widely used decision tree learning algorithms. They are: ID3, ASSISTANT and C4.5.
Also, I found some sample C code for the implementation of ID3 algorithm.
The following is the sample source code for implementation of C4.5 algorithm.
There is a paper talking about "An FPGA Implementation of Decision Tree Classification".
Aindrik's analysis of the 'Implementing Decision Trees...' paper above. Our focus will be on building the data crunching engine, and will assume the tree has already been constructed. We will also focus on 'axis parallel' version (with an eye to the oblique version).
"I found some C code that seems to be the "common" algorithm used on
decision tree analysis. Seems to be based on C4.5 classification
algorithm, and then updated to C5.0.
Project Literature Search
Mon. Nov 14th: Be prepared to discuss the paper identified in Lab 5 above. Please send me links (or the code itself) of any software implementations you discover that are available on the web.
Mon. Nov. 21st: A working version of the decision tree implemented in C on the microblaze.
Wed. Nov. 30th: A working version of the decision tree implemented in VHDL as a state machine. This is the base architecture where you are targeting correct functionality (no optimizations please).
Wed. Dec. 14th: Final version of your optimized decision tree algorithm.