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A language for describing the structural, physical and behavioral characteristics of digital systems.
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Execution of a VHDL program results in a simulation of the digital system.
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Allows us to validate the design prior to fabrication.
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The definition of the VHDL language provides a range of features that support simulation of digital systems.
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VHDL supports both
structural
and
behavioral
descriptions of a system at multiple levels of abstraction.
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Structure and behavior are complementary ways of describing systems.
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A description of the
behavior
of a system says nothing about the
structure
or the components that make up the system.
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There are many ways in which you can build a system to provide the same behavior.
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Reference: "VHDL Starter's Guide", Sudhakar Yalamanchili, Prentice Hall
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VHDL allows you to specify:
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The components of a circuit.
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Their interconnection.
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The behavior of the components in terms of their input and output signals.
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What are its behavioral properties of the half-adder circuit ?
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The
event
on
a
, from 1 to 0, changes the outputs after a 5ns
propagation
delay.
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Both gates (and wires) have inertia or a natural resistance to change.
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A third property of this circuit is concurrency.
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Both the
xor
and
and
gate compute new output values concurrently when an input changes state.
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These new events may go on to initiate the computation of other events in other parts of the circuit, e.g.
s1
and
s3
.
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Data driven system
: Events on signals lead to computations that may generate events on other signals.
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We can view VHDL as a programming language for describing the generation of events in digital systems supported by a
discrete event simulator
.
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A
discrete event simulator
executes VHDL code, modeling the passage of time and the occurrence of events at various points in time.
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It maintains an event list data structure to keep track of the order of all future events in the circuit.
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Advance simulation clock to time of next event, update signals receiving values.
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Evaluate all components affected by signal updates and schedule new events.
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Signals
: Like variables in a programming language such as C, signals can be assigned values, e.g., 0, 1, Z.
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However, signals also have an associated
time value
.
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A signal receives a value at a specific point in time and retains that value until it receives a new value at a future point in time.
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The sequence of values assigned to a signal over time is the
waveform
of the signal.
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A variable always has one current value.
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At any instant in time, a signal may be associated with several
time-value
pairs.
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Design entity: A component of a system whose behavior is to be described and simulated.
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Two components to the description:
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The interface to the design:
entity
declaration.
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The internal behavior of the design:
architecture
construct.
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Entity example for half adder:
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half_adder
is the name given to the design entity.
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The input and outputs signals;
a
,
b
,
sum
and
carry
, are referred to as
ports
.
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Each port has a type,
bit
and
bit_vector
can assume values of 0 and 1.
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Each port has a mode;
in
,
out
or
inout
(bidirectional signals).
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Bit vectors are specified as:
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A
and
B
are 32 bits long with the most significant bit as 31.
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A more general definition of
bit
and
bit_vector
are
std_logic
and
std_logic_vector
, which can assume more than just 0 and 1.
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Concurrent statements
:
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Signal assignment statements specify the new value and the time at which the signal is to acquire this value.
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The textual order of the concurrent signal assignment statements (CSAs) do NOT effect the results.
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We can also use (local) signals internal to the architecture, e.g.,
s1
,
s2
and
s3
in the full adder circuit.
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The following statements are also legal:
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A
driver list
that specifies a waveform.
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This statement generates a set of
transactions
(time-value pairs) to be carried out at distinct times in the future.
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Conditional Signal Assignment Statement
:
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The first conditional found to be true determines the value transferred to the output.
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The
Selected Signal Assignment Statement
behaves similarly.
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Processes are used:
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For describing component behavior when they cannot be simply modeled as delay elements.
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To model systems at high levels of abstraction.
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Process incorporate conventional programming language constructs.
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A process is a
sequentially
executed block of code, which contains.
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arrays and queues.
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Variable assignments, e.g.,
x
:=
y
, which, unlike signals, take effect immediately.
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if-then-else
and loop statements to control flow.
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Signal assignments to external signals.
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Processes contain
sensitivity lists
in which signals are listed, which determine when the process executes.
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In reality, CSAs are also processes without the
process
,
begin
and
end
keywords.
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Looping constructs include the
for
and
while
statements, e.g.,
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The loop
index
is implicitly declared, local to the loop and cannot be changed.
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Processes are executed once upon initialization.
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Thereafter, they are executed in a data-driven manner by either:
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an event on one or more signals in the
sensitivity list
.
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waiting for the occurrence of specific event using a
wait
statement.
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The
wait
statement specifies the conditions under which a process may resume execution after being suspended, e.g.,
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wait for
time expression
; -- wait for a specified time interval.
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wait on
signal
; -- wait on a signal(s).
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wait until
condition
; -- wait until
condition
becomes true;
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The first and third form allow processes to model components that are not necessarily data driven.
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wait
statements also allow processes to suspend at multiple points, and not just at the beginning.
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For example, a positive edge-triggered flip-flop:
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Note attribute
Clk
'
event
which is true when an event (rising or falling edge) occurs on signal
Clk
.
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A D flip-flop with asynchronous reset (R) and set (S) inputs given in reference.
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A state machine (Mealy machine):
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Combinational part implemented in one process, sensitive to events on the input signals or state variables.
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Sequential part implemented in a second process, sensitive to the rising edge of the clock.
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Structural model: A description of a system in terms of the interconnection of its components, rather than a description of what each component does.
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A structural model does NOT describe how output events are computed in response to input events.
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How do we simulate the circuit ?
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Behavioral models of each component are assumed to be provided.
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A VHDL structural description must possess:
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The ability to define the list of components.
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The definition of a set of signals to be used to interconnect them.
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The ability to uniquely label (distinguish between) multiple copies of the same component.
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A structural description of a full adder:
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A state machine of a bit-serial adder:
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A structural description of a bit-serial adder:
