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  • >August 23 seminar: Future of Semiconductors: A Co-Design Approach for Materials, Devices, and Systems

August 23 seminar: Future of Semiconductors: A Co-Design Approach for Materials, Devices, and Systems

August 22, 2024

Photo: Payman Zarkesh-Ha

August 23, 2024

Future of Semiconductors: A Co-Design Approach for Materials, Devices, and Systems

Payman Zarkesh-Ha,Department of Electrical and Computer Engineering, UNM

3:00 pm, Department of Electrical and Computer Engineering, UNM
Online Guests: Contact Prof. Osiński <osinski@chtm.unm.edu> for a Zoom link

Abstract: Semiconductor industry has improved beyond imagination over the past 50 years. Today, AMD’s MI300X GPU has the largest transistor count totaling 153 billion transistors built on TSMC's 5 nm process. This improvement of eight-orders in magnitude of added capability (transistor count) is unheard of in any other industry worldwide. Although the semiconductor industry has made significant efforts over the years to get over the hurdles while scaling transistors, we are now reaching the physical limits of silicon, where a transistor contains only a few silicon atoms. The question is now “What is the future of semiconductors over the next 50 years?” The objective of this talk is to address this question by building a research team to develop a co-design scheme that will pave the way to the creation of a novel synthetic material using semiconductor nanowires in a reconfigurable neuromorphic integrated circuit that can potentially be a revolutionary breakthrough in semiconductor industry by breaking the existing physical limits in integrated circuits.

Bio: Dr. Payman Zarkesh-Ha is a Professor in the ECE Department and Director of the Center for High Technology Materials (CHTM) at UNM. He received his MS degree in Electrical and Computer Engineering from Sharif University, Tehran, Iran in 1994, and his Ph.D. degree in Electrical and Computer Engineering from Georgia Institute of Technology, Atlanta, GA, in 2001. Prior to joining UNM in 2006, he was a Senior Research Engineer with LSI Logic Corporation, Milpitas, CA, where he worked on interconnect architecture design for the next ASIC generations. His research interests include statistical modeling of nanoelectronic devices and systems, design for manufacturability, as well as low-power and highperformance VLSI design. He has published over 125 refereed papers and holds 22 issued patents in this field.